1. Field of the Invention
The present invention relates to a high-level synthesis apparatus, a high-level synthesis system, and a high-level synthesis method.
2. Related Art
As semiconductor integrated circuits have grown smaller, the scale of the system LSI which can be mounted on a single chip has increased. An example of a known method for designing a large-scale system efficiently in a short period of time is high-level synthesis in which a behavioral description describing only the behavior of the system (logic circuit) is created using a high-level language such as the C language, and a RTL (Register Transfer Level) description including hardware information such as clock cycles, registers and operators is synthesized from the behavioral description.
In high-level synthesis, logic circuit design is performed based on indicators for which static analysis is simple, such as area and delay times, but power consumption which is a dynamic characteristic is not taken into account. A well-known technique for lowering the power consumption of logic circuits is to stop supplying the clock using gated clock circuits. However, if gated clock circuits are employed in all the logic circuits, the scale of the circuit increases. Moreover, for the logic circuits with only short intervals between periods of operation, the clock supply can rarely be stopped and the saving in power consumption is small.
Conventional high-level synthesis thus had a problem in that it was not possible to design logic circuits offering significant power saving while suppressing increases in circuit scale.